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關注：1
2013-05-23 12:21
求翻譯：采用六個共陰極的數(shù)碼管,其公共端與138譯碼器的六個輸出端對應相連,譯碼器的輸入端與FPGA芯片的特定引腳相連,由外部輸入時鐘控制信號和秒計數(shù)信號,計數(shù)譯碼過程通過在QuartusII軟件設計由FPGA芯片來完成。動態(tài)數(shù)碼掃描顯示方式是利用了人眼的視覺暫留效應,把六個數(shù)碼管按一定順序(從左至右或從右至左)進行點亮,當點亮的頻率(即掃描頻率)不大時,我們看到的是數(shù)碼管逐個點亮,而當點亮頻率足夠大,超過人眼的分辨頻率,我們將看到它們全部同時穩(wěn)定顯示(點亮),與傳統(tǒng)方式得到的視覺效果完全一樣。是什么意思？ 待解決
 懸賞分：1
- 離問題結束還有
采用六個共陰極的數(shù)碼管,其公共端與138譯碼器的六個輸出端對應相連,譯碼器的輸入端與FPGA芯片的特定引腳相連,由外部輸入時鐘控制信號和秒計數(shù)信號,計數(shù)譯碼過程通過在QuartusII軟件設計由FPGA芯片來完成。動態(tài)數(shù)碼掃描顯示方式是利用了人眼的視覺暫留效應,把六個數(shù)碼管按一定順序(從左至右或從右至左)進行點亮,當點亮的頻率(即掃描頻率)不大時,我們看到的是數(shù)碼管逐個點亮,而當點亮頻率足夠大,超過人眼的分辨頻率,我們將看到它們全部同時穩(wěn)定顯示(點亮),與傳統(tǒng)方式得到的視覺效果完全一樣。
問題補充： |
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2013-05-23 12:21:38
Six common cathode digital tube, six of its public side and 138 decoder output corresponding connected to the input of the decoder and fpga chip specific pins, counting from the external input clock control signal and second signal count decoding process through in quartusii software design fpga chi
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2013-05-23 12:23:18
With a total of 6 CC of the digital tube, the public side of the encoder 138 with 6 output port corresponding to the input translator FPGA chip with a specific pin connected to control by an external input clock signal and second signal, the counter counts in decoding process QuartusII FPGA software
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2013-05-23 12:24:58
Uses six common cathodes the nixietubes, its public end is connected with 138 decoder six out-port correspondences, the decoder input end and the FPGA chip specific pin is connected, by exterior input clock controlling signal and the second counting signal, the counting decoding process through comp
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2013-05-23 12:26:38
Digital with six altogether cathode tube, public port corresponding to the six of the 138 decoder output connected to the decoder inputs are connected to specific pins of the FPGA chip, controlled by an external input clock signal and seconds count signals, count decoding process done by QuartusII s
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2013-05-23 12:28:18
正在翻譯，請等待...
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