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關(guān)注：1
2013-05-23 12:21
求翻譯：本文綜合考慮了組合導(dǎo)航系統(tǒng)對(duì)硬件平臺(tái)性能的各項(xiàng)要求，設(shè)計(jì)了以雙DSP+FPGA為核心的硬件平臺(tái)，成功實(shí)現(xiàn)了導(dǎo)航系統(tǒng)硬件平臺(tái)的各種功能。文中采用了兩塊高性能DSP為運(yùn)算處理核心，輔以FPGA作為前端元件，實(shí)現(xiàn)數(shù)據(jù)采集的功能，為DSP擴(kuò)展串口資源。兩塊DSP分別承擔(dān)了捷聯(lián)慣導(dǎo)解算與組合卡爾曼濾波的功能，兩者通過(guò)同步串口通信達(dá)到協(xié)調(diào)工作。是什么意思？ 待解決
 懸賞分：1
- 離問(wèn)題結(jié)束還有
本文綜合考慮了組合導(dǎo)航系統(tǒng)對(duì)硬件平臺(tái)性能的各項(xiàng)要求，設(shè)計(jì)了以雙DSP+FPGA為核心的硬件平臺(tái)，成功實(shí)現(xiàn)了導(dǎo)航系統(tǒng)硬件平臺(tái)的各種功能。文中采用了兩塊高性能DSP為運(yùn)算處理核心，輔以FPGA作為前端元件，實(shí)現(xiàn)數(shù)據(jù)采集的功能，為DSP擴(kuò)展串口資源。兩塊DSP分別承擔(dān)了捷聯(lián)慣導(dǎo)解算與組合卡爾曼濾波的功能，兩者通過(guò)同步串口通信達(dá)到協(xié)調(diào)工作。
問(wèn)題補(bǔ)充： |
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2013-05-23 12:21:38
Considering the requirements of the integrated navigation system on the hardware platform performance, design the hardware platform as the core of dual dsp + fpga, successful implementation of the various functions of the navigation system hardware platform. Using two high-performance dsp for comput
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2013-05-23 12:23:18
This article has an integrated consideration of hardware platforms combined navigation system performance requirements, design a double-DSP + FPGA as the core to the hardware platform, has succeeded in achieving the various features navigation system hardware platform. used in high-performance DSP t
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2013-05-23 12:24:58
This article overall evaluation mixed navigation system to hardware platform performance each request, has designed take double DSP+FPGA as the core hardware platform, the success has realized guidance system hardware platform each kind of function.In the article has used two high performance DSP is
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2013-05-23 12:26:38
This article considering the integrated navigation system on the performance of the hardware platform requirements, hardware platform design with dual DSP+FPGA as the core, successful implementation of the various features of the hardware platform for the navigation system. Using two high-performanc
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2013-05-23 12:28:18
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